CHIPS Alliance launches the SV Tools Project for open source development of SystemVerilog/UVM codebases

CHIPS Alliance, an organization operating under the Linux Foundation with the aim to foster collaborative, open source development in the silicon hardware design ecosystem, is happy to introduce the SV Tools Project facilitating the development of high-quality, open source tooling for working with SystemVerilog (SV) codebases. With support from CHIPS Alliance members and collaborators, we’ve grouped together a suite of open source tools used for development of hardware leveraging SystemVerilog and the most common SV design verification methodology, UVM. The effort aims to provide better visibility and support for both project maintainers and users, and foster a more coherent open source tooling experience for various aspects of ASIC development and verification with SV/UVM.