Constrained randomization in Verilator

Digital design verification often utilizes the so-called constrained randomization functionality offered by SystemVerilog, where in order to efficiently test designs with random but still correct data, a digital logic designer can put constraints in place. This allows verification tests to run shorter by focusing the validation of the design’s behavior on input that the designer considers useful and interesting. A few months ago Antmicro introduced constrained randomization to Verilator - another significant milestone on the way towards full open source support for SystemVerilog and…