Initial assertion control support in Verilator

Antmicro is continuously working on improving productivity of ASIC design and verification workflows using open source tools as leaders of the CHIPS Alliance Tools Workgroup, as well as for customer and R&D projects. Extending Verilator with new verification features is a prominent example of such efforts, with the latest notable improvements including initial support for UVM testbenches , the astsee tool for Verilator process and AST analysis and constrained randomization . In this article, Antmicro introduces initial support for global assertion control ( already part of mainline Verilator…