Verilator Model Generation Performance Improvements and Initial Multithreaded Verilation Support

Verilator can boast the status of one of the most widely used free and open source digital design tools for ASIC and FPGA development. To stay on top of the ever-increasing complexity of ASIC and FPGA devices, as users and contributors, Antmicro, a CHIPS Alliance member and part of the Tools Workgroup , has been actively working on improving the tool and its ecosystem, including adding co-simulation capabilities with Renode , adding support for SystemVerilog UVM testbenches to Verilator , or improving scalability for very large designs .