Integrating the Language Server Protocol in Verible

A more collaborative, open and software driven ASIC design methodology pioneered by the CHIPS Alliance requires an open source tooling stack to enable sharing of workflows, artifacts and fostering a free exchange of insights and improvements. While internally often using new design methodologies and languages such as Migen, Chisel or XLS, Antmicro is conscious of the fact that a lot of the world’s ASIC development involves SystemVerilog and UVM, and so we are working on bridging traditional and new ASIC development methodologies as described in a recent blog note .