Towards UVM: Using Coroutines for Low-overhead Dynamic Scheduling in Verilator

This post was originally published at Antmicro . Verilator is a popular open source SystemVerilog simulator and one of the key tools in the ASIC and FPGA ecosystem, which Antmicro is actively using and developing, e.g. by enabling co-simulation with Renode or Cocotb integration . It’s also one of the fastest available HDL simulators, including proprietary alternatives.