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Forum Post: Automatic Chaining in Layout GXL

calendar_today October 23, 2026 person Dhruv N Patel domain cadence

Hi everyone, I’m working in Cadence Virtuoso Layout GXL 6.1.8 with two NMOS transistors, M0 and M1, each having a multiplier of 2 (m = 2) and a single finger (nf = 1). The schematic shown is just a simplified example to illustrate the issue, not an actual circuit implementation. For the purpose of interdigitation , I’m trying to place one physical transistor from M0 next to one from M1 and overlap their adjacent source diffusion regions to create a shared source diffusion, since both sources are connected to the same net (GND).

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